950B Memory Architecture Pattern

Full-stage PTO memory architecture preview built from the shared aic-core-object and aiv-core-object renderers. The chip-level routes follow the official AIC/AIV split memory model, and the 950-specific direct CV lanes are added from the local 950 slide extracts.

pattern id: memory-architecture-layout default preset: ascend950b contract: full-stage DOM shell + shared AIC/AIV renderers + SVG route overlay