Ascend 950B Memory Architecture Pattern
1 AIC + 2 AIV；GM/L2 在 AI Core 外；L0C→UB 和 UB→L1 作为 950 直接 CV lanes。
Local GMpayload source / sink
SDMAasync GM↔GM DMA
UnifiedBus950 IO interconnect
URMAremote memory path
Remote GMtarget rank memory
AIV Controlsession / wait / test
CCUcollective offload
Memory SliceCCU cache
Reduce Enginesum / max / min
Result GMwriteback